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mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 description application main memory unit for computers, microcomputer memory. preliminary some of contents are subject to change without notice. 1 1pin 10pin 11pin 40pin 41pin 84pin front side 85pin 94pin 95pin 124pin 125pin 168pin back side the mh16s72pjb is 16777216 - word x 72-bit synchronous dram module. this consist of nine industry standard 16m x 8 synchronous drams in tsop. the mounting of tsop on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. this is a socket-type memory module ,suitable for easy interchange or addition of module. features type name 6ns (cl = 2, 3) MH16S72PJB-7 utilizes industry standard 16m x 8 synchronous drams in tsop package , industry standard resistered buffer in tssop package and industry standard pll in tssop package single 3.3v +/- 0.3v supply lvttl interface burst length 1/2/4/8/full page(programmable) burst write / single write(programmable) auto precharge / all bank precharge controlled by a10 auto refresh and self refresh 4096 refresh cycles every 64ms max. frequency clk access time [component level] 100mhz discrete ic and module design conform to pc/100 specification. (module spec. rev. 1.0 and spd 1.2a) 6ns (cl = 3) mh16s72pjb-8 100mhz
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 2 nc = no connection pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 /s2 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 vdd 48 nc 90 vdd 132 nc 7 dq4 49 vdd 91 dq36 133 vdd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vdd 101 dq45 143 vdd 18 vdd 60 dq20 102 vdd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 cke1 105 cb4 147 rege 22 cb1 64 vss 106 cb5 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vdd 68 vss 110 vdd 152 vss 27 /we0 69 dq24 111 /cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 /s0 72 dq27 114 nc 156 dq59 31 nc 73 vdd 115 /ras 157 vdd 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 ck2 121 a9 163 ck3 38 a10 80 nc 122 ba0 164 nc 39 ba1 81 test 123 a11 165 sa0 40 vdd 82 sda 124 vdd 166 sa1 41 vdd 83 scl 125 ck1 167 sa2 42 ck0 84 vdd 126 nc 168 vdd
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 3 ck0 pll ck1 - ck3 terminated vdd vss d0 to d8 d0 to d8 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 d0 dq12 dq13 dq14 dq15 dq8 dq9 dq10 dq11 d1 dq23 dq20 dq21 dq22 dq16 dq17 dq18 dq19 d3 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 d4 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d2 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 d5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 d6 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 d7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 d8 rdqmb0 rdqmb1 rdqmb2 rdqmb3 rdqmb7 rdqmb6 rdqmb5 rdqmb4 /rs0 /rs2 /s0 , /s2 dqmb0 to dqmb7 ba0-ba1 a0-a11 /ras /cas cke0 /we vdd rege ck2 /rs0 , /rs2 rdqmb0 to rdqmb7 rba0-rba1 ra0-ra11 r/ras r/cas rcke0 r/we 10k ba0-ban:d0-d8 a0-a11:d0-d8 /ras: d0-d8 /cas: d0-d8 /we:d0-d8 /we:d0-d8 sa0 sa1 sa2 serial pd scl sda a0 a1 a2 wp 47k
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 pin function input master clock:all other inputs are referenced to the rising edge of ck cke0 input clock enable:cke controls internal clock.when cke is low,internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke e becomes asynchronous input.self refresh is maintained as long as cke is low. /s0,2 input chip select: when /s is high,any command means no operation. /ras,/cas,/w input combination of /ras,/cas,/w defines basic commands. a0-11 input a0-11 specify the row/column address in conjunction with ba.the row address is specified by a0-11.the column address is specified by a0-9.a10 is also used to indicate precharge option.when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, both banks are precharged. ba0-1 input bank address:ba0,1 is not simply ba.ba0,1 specifies the bank to which a command is applied.ba must be set with act,pre,read,write commands dq0-63 cb0-7 input/output data in and data out are referenced to the rising edge of ck dqm0-7 input din mask/output disable:when dqmb is high in burst write.din for the current cycle is masked.when dqmb is high in burst read,dout is disabled at the next but one cycle. vdd,vss power supply power supply for the memory mounted module. ck0 rege output register enable:when rege is low,all control signals and address are buffered. (buffer mode) when rege is high,all control and address are latched. (latch mode) 4
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 basic functions /s chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command ck define basic commands the mh16s72pjb provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. each command is defined by control signals of /ras,/cas and /we at ck rising edge. in addition to 3 signals,/s,cke and a10 are used as chip select,refresh option,and precharge option,respectively. to know the detailed definition of commands please see the command truth table. activate(act) [/ras =l, /cas = /we =h] read(read) [/ras =h,/cas =l, /we =h] write(write) [/ras =h, /cas = /we =l] precharge(pre) [/ras =l, /cas =h,/we =l] auto-refresh(refa) [/ras =/cas =l, /we =cke =h] act command activates a row in an idle bank indicated by ba. read command starts burst read from the active bank indicated by ba.first output data appears after /cas latency. when a10 =h at this command,the bank is deactivated after the burst read(auto-precharge, reada ). write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write(auto-precharge, writea ). pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, both banks are deactivated(precharge all, prea ). pefa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. 5
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 command truth table command mnemonic ck n-1 ck n /s /ras /cas /we ba a10 a0-9 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row adress entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all bank prea h x l l h l v h x column address entry & write write h x l lh h l v l v column address entry & write with auto- precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto precharge reada h x l h l h v h v auto-refresh refa h h l hl l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h lx x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l l l v*1 h =high level, l = low level, v = valid, x = don't care, n = ck cycle number note: 1.a7-9 = 0, a0-6 = mode address 6
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 current state /s /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act bank active,latch ra l l h l ba,a10 pre/prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l ba tbst nop l h l h ba,ca,a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba,ca,a10 write/ writea begin write,latch ca, determine auto-precharge l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea precharge/precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin new read,determine auto-precharge*3 l h l l ba,ca,a10 write/writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal function truth table 7
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 function truth table (continued) current state /s /ras /cas /we address command action write h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin read,determine auto- precharge*3 l h l l ba,ca,a10 write/ writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 8
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 function truth table (continued) current state /s /ras /cas /we address command action pre - h x x x x desel nop(idle after trp) charging l h h h x nop nop(idle after trp) l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea nop*4(idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row h x x x x desel nop(row active after trcd activating l h h h x nop nop(row active after trcd l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- h x x x x desel nop covering l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 9
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 function truth table (continued) current state /s /ras /cas /we address command action re- h x x x x desel nop(idle after trc) freshing l h h h x nop nop(idle after trc) l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode h x x x x desel nop(idle after trsc) register l h h h x nop nop(idle after trsc) setting l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h = hige level, l = low level, x = don't care ba = bank address, ra = row address, ca = column address, nop = no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state.may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and / or date-integrity are not guaranteed. 10
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 function truth table for cke current state ck n-1 ck n /s /ras /cas /we add action self - h x x x x x x invalid refresh*1 l h h x x x x exit self-refresh(idle after trc) l h l h h h x exit self-refresh(idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self-refresh) power h x x x x x x invalid down l h x x x x x exit power down to idle l l x x x x x nop(maintain self-refresh) all banks h h x x x x x refer to function truth table idle*2 h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state = power down any state h h x x x x x refer to function truth table other than h l x x x x x begin ck0 suspend at next cycle*3 listed above l h x x x x x exit ck0 suspend at next cycle*3 l l x x x x x maintain ck0 suspend abbreviations: h = high level, l = low level, x = don't care notes: 1. cke low to high transition will re-enable ck and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only form the all banks idle state. 3. must be legal command. 11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqmb high and nop condition at the inputs. 2. maintain stable power, stable cock, and nop input conditions for a minimum of 500?. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register(mrs). the mode register stores these date until the next mrs command, which may be issue when both banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. 12 r:reserved for future use /s /ras /cas /we ba0,1 a11-0 ck v bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 1 2 4 8 r r r fp 1 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 wm 0 0 ltmode bt bl 0 0 cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 latency mode /cas latency 2 3 r r r r r r 0 1 write mode burst single bit fp: full page
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 command address ck read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4 a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 13
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 absolute maximum ratings symbol parameter condition ratings unit vdd vi vo io pd topr tstg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature with respect to vss with respect to vss with respect to vss ta=25? -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 12 0 ~ 70 -45 ~ 100 v v v ma w ? ? recommended operating condition (ta=0 ~ 70?, unless otherwise noted) symbol vdd vss vih*1 vil*2 parameter supply voltage high-level input voltage all inputs supply voltage low-level input voltage all inputs limits unit min. typ. max. 3.0 0 2.0 -0.3 3.3 0 3.6 0 vdd+0.3 0.8 v v v v capacitance (ta=0 ~ 70?, vdd = 3.3 +/- 0.3v, vss = 0v, unless otherwise noted) symbol ci(a) ci(c) ci(k) ci/o parameter input capacitance, address pin input capacitance, control pin input capacitance, ck0 pin input capacitance, i/o pin test condition limits(max.) unit vi = vss f=1mhz vi=25mvrms 20 20 20 22 pf pf pf pf 14 note) 1.vih(max)=5.5v for pulse width less than 10ns. 2.vil(min)=-1.0v for pulse width less than 10ns.
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 15 ac operating conditions and characteristics (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) symbol parameter test condition limits unit min. max. voh(dc) high-level output voltage(dc) ioh=-2ma 2.4 v vol(dc) low-level output voltage(dc) iol=2ma 0.4 v voh(ac ) high-level output voltage(ac) cl=50pf, ioh=-2ma 2 v vol(ac) low-level output voltage(ac) cl=50pf, iol=2ma 0.8 v ioz off-stare output current q floating vo=0 ~ vdd -10 10 ua ii input current vih=0 ~ vdd+0.3v -10 -10 ua average supply current from vdd (ta=0 ~70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) note1:icc(max) is specified at the output open condition. note2:low power version 1105 43 34 205 1195 1645 34 97 70 70 295 250 -7, -8 test condition limits (max) unit trc=min.tclk=min, bl=1, i ol =min ma cke=l,tclk=min ma cke=clk=l ma ma tclk=min, bl=4, cl=3 aall banks active(discerte) ma trc=min, tclk=min ma cke <0.2v ma tclk=min,cke=h,vih>vcc-0.2v,vil<0.2v symbol icc1 icc2p icc2ps icc2ns icc4 icc5 icc6 icc2n parameter operating current one bank active (discrete) precharge stanby current in power-down mode /cs>vcc-0.2v burst current auto-refresh current self-refresh current clk=l&cke=h,vih>vcc-0.2v,vil<0.2v all input signals are fixed . ma precharge stanby current in non power-down mode /cs>vcc-0.2v ma icc3ps icc3p ma active stanby current in power-down mode ma cke=h, tclk=min icc3ns icc3n ma active stanby current in non power-down mode cke=l, tclk=min cke=l, clk=l cke=h, clk=l 30.4 ma note *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1,2
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 ac timing requirements (ta=0 ~ 70?, vdd = 3.3 +/- 0.3v, vss = 0v, unless otherwise noted) input pulse levels: 0.8v to 2.0v input timing measurement level: 1.4v ck signal 1.4v 1.4v any ac timing is referenced to the input signal crossing through 1.4v. latch mode 16 limits symbol parameter -7 unit min. max. tclk ck cycle time ns tch ck high pulse width 3 10 ns tcl ck low pilse width 3 ns tt transition time of ck 1 10 ns tis input setup time(all inputs) 2 ns tih input hold time(all inputs) 1 ns trc row cycle time 70 ns trcd row to column delay 20 ns tras row active time 50 100000 ns trp row precharge time 20 ns twr write recovery time 10 ns trrd act to act deley time 20 ns tccd col to col delay time 10 ns trsc mode register set cycle time 20 ns tref refresh interval time 64 ms cl=3 tsrx self refresh exit time 10 ns -8 min. max. 3 13 3 1 10 2 1 70 20 50 100000 20 10 20 10 20 64 10 10 cl=4 10 ns tpde power down exit time 10 ns 10
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 buffer mode limits symbol parameter -7 unit min. max. tclk ck cycle time ns tch ck high pulse width 3 10 ns tcl ck low pilse width 3 ns tt transition time of ck 1 10 ns tis input setup time(all inputs) 8 ns tih input hold time(all inputs) 0 ns trc row cycle time 70 ns trcd row to column delay 20 ns tras row active time 50 100000 ns trp row precharge time 20 ns twr write recovery time 10 ns trrd act to act deley time 20 ns tccd col to col delay time 10 ns trsc mode register set cycle time 20 ns tref refresh interval time 64 ms cl=2 switching characteristics (ta=0 ~ 70?, vdd = 3.3 +/- 0.3v, vss = 0v, unless otherwise noted) unit ns ns ns limits symbol parameter -7 min. max. tac access time from ck cl=3 6 ns toh output hold time 3 from ck tolz delay time, output low impedance from ck 0 tohz delay time, output high impedance from ck 3 6 latch mode 17 tsrx self refresh exit time 10 ns -8 min. max. 4 13 4 1 10 8 0 70 20 50 100000 20 10 20 10 20 64 10 10 cl=3 10 ns -8 min. max. 7 3 0 3 6 cl=4 6 6 tpde power down exit time 10 ms 10 *1 note note) 1.if clock rising time is longer than 1ns,(tr /2-0.5ns) should be added to the parameter.
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 1.4v 1.4v dq ck tac toh tohz output load condition v out 50pf 50 w v tt =1.4v dq ck output timing measurement reference point 1.4v 1.4v buffer mode 18 unit ns ns ns limits symbol parameter -7 min. max. tac access time from ck cl=2 6 ns toh output hold time 3 from ck tolz delay time, output low impedance from ck 0 tohz delay time, output high impedance from ck 3 6 -8 min. max. 7 3 0 3 6 cl=3 6 6 *1 note note) 1.if clock rising time is longer than 1ns,(tr /2-0.5ns) should be added to the parameter.
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 write cycle (single bank) bl=4,buffer mode(rege="l") rege 19 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd twr trp trc trcd clk italic parameter indicates minimum case tras a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 write cycle (dual bank) bl=4,buffer mode(rege="l") rege 20 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras twr trp trc trcd d1 d1 d1 d1 x x x 1 trrd y twr 0 x 1 x x x 2 trrd act#1 write#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 write cycle (single bank) bl=4,lacth mode(rege="h") rege 21 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd twr trp trc trcd clk italic parameter indicates minimum case tras a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 write cycle (dual bank) bl=4,latch mode(rege="h") rege 22 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras twr trp trc trcd d1 d1 d1 d1 x x x 1 trrd y twr 0 x 1 x x x 2 trrd act#1 write#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 read cycle (single bank) bl=4,cl=3,buffer mode(rege="l") rege 23 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 read to pre 3 bl allows full data out dqm read latency =2 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 bl=4,cl=3,buffer mode(rege="l") read cycle (dual bank) 24 rege /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 x x x 2 1 cl=3 read#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 read cycle (single bank) bl=4, cl=3,latch mode(rege="h") 25 rege /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 read to pre 3 bl allows full data out dqm read latency =3 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 bl=4,cl=3,latch mode(rege="h") read cycle (dual bank) 26 rege /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 dqm read latency =3 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 x x x 2 1 cl=3 read#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 27 burst write (multi bank) with auto-precharge bl=4,buffer mode(rege="l") rege /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 with autoprecharge act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd d1 d1 d1 d1 x x x 1 trrd y x 1 x x x trrd act#1 write#1 with autoprecharge bl-1+ twr + trp y 1 d1 trcd act#1 write#1 clk bl-1+ twr + trp italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 28 burst write (multi bank) with auto-precharge bl=4,latch mode(rege="h") rege /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 with autoprecharge act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd d1 d1 d1 d1 x x x 1 trrd y x 1 x x x trrd act#1 write#1 with autoprecharge bl-1+ twr + trp y 1 trcd act#1 write#1 clk bl-1+ twr + trp italic parameter indicates minimum case a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 29 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 with auto-precharge act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 cl=3 read#1 with auto-precharge act#1 bl+ trp bl+ trp x x x 1 y 1 clk q0 cl=3 trcd italic parameter indicates minimum case burst read (multi bank) with auto-precharge bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 30 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 with auto-precharge act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd cl=3 dqm read latency =3 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 cl=3 read#1 with auto-precharge act#1 bl+ trp bl+ trp x x x 1 y 1 clk q0 cl=3 trcd italic parameter indicates minimum case burst read (multi bank) with auto-precharge bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 31 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 act#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd d1 d1 d1 d1 y y 0 write#1 clk x x x 1 trrd 1 y d0 d0 d0 d0 d0 d0 d0 act#1 write#0 italic parameter indicates minimum case page mode burst write (multi bank) bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 32 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 act#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd d1 d1 d1 d1 y y 0 write#1 clk x x x 1 trrd 1 y d0 d0 d0 d0 d0 d0 act#1 write#0 italic parameter indicates minimum case page mode burst write (multi bank) bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 33 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q1 q1 q1 q1 y y 0 read#1 clk x x x 1 trrd 1 y q0 q0 q0 q0 act#1 read#0 q0 cl=3 cl=3 cl=3 dqm read latency=2 italic parameter indicates minimum case page mode burst read (multi bank) bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 34 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q1 q1 q1 q1 y y 0 read#1 clk x x x 1 trrd 1 y q0 q0 q0 q0 act#1 read#0 q0 cl=3 cl=3 cl=3 dqm read latency=3 italic parameter indicates minimum case page mode burst read (multi bank) bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 35 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 write#1 clk x x x 1 trrd 1 y d0 d0 d1 d1 q0 q0 q0 act#1 write#0 y y 0 0 0 y tccd cl=3 write#0 read#0 burst write can be interrupted by write or read of any active bank. italic parameter indicates minimum case write interrupted by write / read bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 36 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 write#1 clk x x x 1 trrd 1 y d0 d0 d1 d1 q0 q0 q0 act#1 write#0 y y 0 0 0 y tccd cl=3 write#0 read#0 burst write can be interrupted by write or read of any active bank. italic parameter indicates minimum case write interrupted by write / read bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 37 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 d0 d0 y y 0 read#1 clk x x x 1 trrd 0 y q0 q0 q1 q1 act#1 read#0 q0 dqm read latency=2 0 y 1 y burst read can be interrupted by read or write of any active bank. read#0 read#0 blank to prevent bus contention italic parameter indicates minimum case read interrupted by read / write bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 38 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 d0 y y 0 read#1 clk x x x 1 trrd 0 y q0 q0 q1 q1 act#1 read#0 q0 dqm read latency=3 0 y 1 y burst read can be interrupted by read or write of any active bank. read#0 read#0 blank to prevent bus contention italic parameter indicates minimum case read interrupted by read / write bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd write#1 clk x x x 1 trrd 1 d1 d1 d1 d1 d1 act#1 y 1 1 y burst write is not interrupted by precharge of the other bank. 0 x x x 1 pre#1 pre#0 act#1 write#1 burst write is interrupted by precharge of the same bank. italic parameter indicates minimum case write interrupted by precharge bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11 39
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd write#1 clk x x x 1 trrd 1 d1 d1 d1 d1 d1 act#1 y 1 1 y burst write is not interrupted by precharge of the other bank. 0 x x x 1 pre#1 pre#0 act#1 write#1 burst write is interrupted by precharge of the same bank. italic parameter indicates minimum case write interrupted by precharge bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11 40
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd y 1 pre#1 clk x x x 1 trrd q1 q1 act#1 pre#0 q0 dqm read latency=2 1 y 1 burst read is not interrupted by precharge of the other bank. 0 x x x 1 trcd trp read#1 act#1 read#1 burst read is interrupted by precharge of the same bank. italic parameter indicates minimum case read interrupted by precharge bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11 41
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd y 1 pre#1 clk x x x 1 trrd q1 q1 act#1 pre#0 q0 dqm read latency=3 1 y 1 burst read is not interrupted by precharge of the other bank. 0 x x x 1 trcd trp read#1 act#1 read#1 burst read is interrupted by precharge of the same bank. italic parameter indicates minimum case read interrupted by precharge bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11 42
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 mode register setting /cs /ras /cas /we cke ba0,1 dq auto-ref (last of 8 cycles) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 y 0 clk trc d0 mode register setting m 0 x x x 0 trcd trsc act#0 write#0 d0 d0 d0 italic parameter indicates minimum case rege a0-9 a10 dqm a11 43
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 auto-refresh @bl=4 /cs /ras /cas /we cke ba0,1 dq auto-refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk trc before auto-refresh, all banks must be idle state. y 0 d0 x x x 0 trcd act#0 write#0 d0 d0 d0 after trc from auto-refresh, all banks are idle state. italic parameter indicates minimum case rege a0-9 a10 dqm a11 44
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 45 self-refresh /cs /ras /cas /we cke ba0,1 dq self-refresh entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk before self-refresh entry, all banks must be idle state. x x x 0 self-refresh exit act#0 after trc from self-refresh exit, all banks are idle state. trc tsrx clk can be stopped cke must be low to maintain self-refresh italic parameter indicates minimum case rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 46 dqm write mask @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 y 0 d0 d0 d0 act#0 write#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked italic parameter indicates minimum case bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 47 dqm write mask @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 y 0 d0 d0 d0 act#0 write#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked italic parameter indicates minimum case bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 48 dqm read mask @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 y 0 q0 q0 q0 act#0 read#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked dqm read latency=2 italic parameter indicates minimum case bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 dqm read mask @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 y 0 q0 q0 q0 act#0 read#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked dqm read latency=3 italic parameter indicates minimum case bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11 49
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 power down /cs /ras /cas /we cke ba0,1 dq 0 precharge all act#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk x x x standby power down active power down cke latency=1 italic parameter indicates minimum case rege a0-9 a10 dqm a11 50
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 clk suspend @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 act#0 write#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y d0 d0 d0 d0 clk suspended clk suspended cke latency=1 cke latency=1 italic parameter indicates minimum case bl=4,buffer mode(rege="l") rege a0-9 a10 dqm a11 51
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 clk suspend @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 act#0 write#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y d0 d0 d0 d0 clk suspended clk suspended cke latency=2 cke latency=2 italic parameter indicates minimum case bl=4,latch mode(rege="h") rege a0-9 a10 dqm a11 52
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 serial presence detect table i byte function described spd enrty data spd data(hex) 0 defines # bytes written into serial memory at module mfgr 128 80 1 total # bytes of spd memory device 256 bytes 08 2 fundamental memory type sdram 04 3 # row addresses on this assembly a0-a11 0c 4 # column addresses on this assembly a0-a9 0a 5 # module banks on this assembly 1bank 01 6 data width of this assembly... x72 48 7 ... data width continuation 0 00 8 voltage interface standard of this assembly lvttl 01 9 sdram cycletime at max. supported cas latency (cl). a0 cycle time for cl=3 10 sdram access from clock 6ns 60 tac for cl=3 11 dimm configuration type (non-parity,parity,ecc) ecc 02 12 refresh rate/type self refresh(15.625us) 80 13 sdram width,primary dram x8 08 14 error checking sdram data width x8 08 15 minimum clock delay,back to back random column addresses 1 01 16 burst lengths supported 1/2/4/8/full page 8f 17 # banks on each sdram device 4bank 04 18 cas# latency 2/3 06 19 cs# latency 0 01 20 write latency 0 01 21 sdram module attributes buffered,registered 1f 22 sdram device attributes:general precharge all,auto precharge write1/read burst 0e 23 sdram cycle time(2nd highest cas latency) cycle time for cl=2 13ns d0 24 sdram access form clock(2nd highest cas latency) 7ns 70 tac for cl=2 25 sdram cycle time(3rd highest cas latency) n/a 00 n/a 00 26 sdram access form clock(3rd highest cas latency) 27 precharge to active minimum 20ns 14 28 row active to row active min. 20ns 14 10ns -8 -8 -7 10ns a0 6ns 60 -7 29 ras to cas delay min 20ns 14 30 active to precharge min 50ns 32 53
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 serial presence detect table ii 31 density of each bank on module 128mbyte 20 36-61 superset information (may be used in future) option 00 62 spd revision 63 checksum for bytes 0-62 check sum for -8 87 64-71 manufactures jedec id code per jep-108e mitsubishi 1cffffffffffffff 72 manufacturing location miyoshi,japan 01 tajima,japan 02 nc,usa 03 germany 04 73-90 manufactures part number 91-92 revision code pcb revision rrrr 93-94 manufacturing date year/week code yyww 95-98 assembly serial number serial number ssssssss 99-125 manufacture specific data option 00 126 intetl specification frequency 100mhz 64 127 intel specification cas# latency support 128+ unused storage locations open 00 32 command and address signal input setup time 2ns 20 20 33 command and address signal input hold time 1ns 10 34 data signal input setup time 2ns 35 data signal input hold time 1ns 10 rev 1.2a 12 check sum for -7 47 MH16S72PJB-7 4d483136533732504a422d37202020202020 8f 54 mh16s72pjb-8 cl=2/3,ap,ck0 4d483136533732504a422d38202020202020
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 133.35 17.78 3.9max 4.18min 8.89 11.43 3 24.495 6.35 36.83 127.35 42.18 6.35 54.61 1.27 38.1 3 3 4 55 4.05min 1.27
mitsubishi electric 1207959552-bit ( 16777216-word by 72-bit ) synchronous dynamic ram MH16S72PJB-7, -8 mitsubishi lsis preliminary preliminary spec. spec. 11/jan. /1999 mit-ds-0302-0.0 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.all information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 6.if these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 7.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. 56

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